with conventional techniques; there typically is provided a wafer generally prepared for a MOS (metal oxide silicon) semiconductor device. For isolating active areas of the device elements, as shown in FIG. 1(a), pad silicon oxide layer 11 is formed by application of a thermal oxidation process in order to relieve stress created during field oxidation, which is induced in silicon substrate 10 due to the difference of thermal expansion between a later-formed silicon nitride layer and silicon substrate 10. The stress relief is provided by utilizing the thermal viscous flow of the silicon oxide layer.
Then, silicon nitride layer 12 is formed by application of a low pressure chemical vapor deposition process to prevent the oxidation of silicon substrate 10 during field oxidation.
Thereafter, a photo etching process is applied to pattern silicon nitride layer 12 and pad silicon oxide layer 11, and the resulting pattern distinguishes areas where unit elements are to be formed (active regions) and areas where isolating layers (field oxide) are to be formed (field regions) (for clarity, the figures and the discussion refer sometimes to "active region" and "field region", although, as is known in the art, in actual devices a plurality of action and field regions are formed on the substrate). Then, a first field ion implantation process is carried out into field surface regions of silicon substrate 10 (the ion implanted regions being indicated by a dashed line in FIG. 1).
Next, as shown in FIG. 1(b), second silicon nitride layer 13 is deposited in a thin thickness, and CVD (chemical vapor deposition) SiO.sub.2 layer 14 is deposited to self align a thin offset nitride layer extending from the active nitride layer on the active region.
Then, as shown in FIG. 1(c), SiO.sub.2 layer 14 is etched back to form CVD SiO.sub.2 side wall 14a, and second silicon nitride layer 13 is etched back. Silicon substrate 10 is further etched to a shallow depth as illustrated. Thereafter, a second field ion implantation process is performed to form channel stop doping on the etched lower region.
Next, as shown in FIG. 1(d), silicon oxide side wall 14a is stripped by immersion in an etching solution (such as HF). Then as shown in FIG. 1(e), the field oxidation process is performed to grow field oxide layer 15, thereby completing the isolation process. After these steps, a normal MOS type semiconductor manufacturing process is carried out.
Such a conventional technique has a number of disadvantages. The thickness of the nitride layer has to be over 2000 Angstroms in order to secure the height difference which is needed to form the side wall which is in turn required to self align the offset nitride for extending the silicon nit ride layer of the active silicon nitride layer to beneath the side wall. Accordingly, the thickness of the pad silicon oxide layer which is provided for stress-relieving during the field oxidation typically has to be over 500 Angstroms in thickness. After the field oxidation, the silicon nitride layer is removed, and the silicon oxide layer of the active region has to be removed by at least500 Angstroms, and consequently, damage to the silicon oxide layer of the field region can become severe.
Further, for growth of the field oxide layer, the thickness of the field oxide layer has to be very large if there is to be secured a proper threshold voltage (Vth) for the field transistor which uses the field oxide between the active regions as the gate oxide. Consequently, a large amount of stress is built up during the field oxidation, with the possible consequence that crystal defects may occur.
In addition, a thick silicon nitride layer is used as the oxidizing mask, and, therefore, this can result in crystal defects in the silicon substrate. As a result, the electrical characteristics and the reliability of the device as well as the manufacturing yield of the products may be impaired.